1. Field of the Invention
The present invention relates to a current driven D/A converter and its bias circuit.
2. Description of Related Art
In a current driven D/A converter composed of MOS transistors, current switches are implemented by transistors. As shown in FIG. 7, a conventional current driven D/A converter, which employs NMOS transistors for current switches, uses a ground voltage as an OFF control voltage for turning off the current switches (see non-patent document 1, for example). To switch from ON to OFF state or vice versa, the gate electrodes of the switching transistors are supplied with an amplitude greater than a voltage at which the current switch actually switches off.
Accordingly, as shown in FIG. 8, charge injections greater than necessary takes place via parasitic capacitances of the switching transistors. This causes noise that brings about accuracy degradation and conversion rate restriction of the D/A converter.
Furthermore, as shown in FIG. 9, in the switching transistor that is turning off from the ON state, charges stored in the parasitic capacitance in the ON state flow into a ground terminal at the moment it turns off. Thus, large charge discharge current flows instantaneously into the ground terminal. Because of the current and parasitic resistance and parasitic inductance of the ground terminal, the ground terminal voltage fluctuates, which brings about performance degradation of the D/A converter.
Likewise, in the switching transistors composed of PMOS transistors, large charge injections and noise of the power supply voltage occur.
In addition, as shown in FIG. 10, in a current source (M1 and M2) connected in cascode, both the current source transistor M1 and cascode transistor M2 are used in the saturation region. Thus, the bias voltage of the cascode transistor M2 must be set in such a manner that the current source transistor M1 is saturated. Accordingly, the diode connection transistor M3 has been used as a bias circuit. When the transistors M2 and M3 have the same threshold voltage, the channel width/channel length ratio (W/L)3 of the transistor M3 for saturating the transistor M1 is obtained by the following expression (1).
                                          (                          W              /              L                        )                    ⁢          3                <                                            (                              1                                  1                  +                                      1                    /                                          K                                                                                  )                        2                    ⁢                      (                          W              /              L                        )                    ⁢          1                                    (        1        )            where K=(W/L)2/(W/L)1. In this case, since (W/L)3 is determined by device sizes of (W/L)1 and (W/L)2, it can be determined accurately in a semiconductor integrated circuit.
In an actual circuit, however, the threshold voltages Vth2 and Vth3 of the transistors M2 and M3 differ because of the substrate bias effect. Thus, the condition of (W/L)3 for operating the transistor M1 in the saturation region is given by the following expression, which means that the condition depends on I0, Vth2 and Vth3.
                                          (                          W              /              L                        )                    ⁢          3                <                  1                                    (                                                (                                                            (                                              1                        +                                                  1                          /                                                      K                                                                                              )                                        ⁢                                          1                                                                                                    (                                                          W                              /                              L                                                        )                                                    ⁢                          1                                                                                                      )                                +                                                      1                                                                  2                        ⁢                        I0                                                                              ⁢                                      (                                          Vth2                      -                      Vth3                                        )                                                              )                        2                                              (        2        )            where Iout=Iref is set at I0. Accordingly, the bias voltage value must be generated with leaving sufficient margin considering fabrication variations in I0, Vth2 and Vth3. Thus, it is difficult for a low voltage circuit or a circuit with a small M2 drain voltage to achieve the conditions.
Non-patent document 1: “An 80-MHZ 8-bit CMOS D/A Converter”, IEEE J. Solid-State Circuits, vol. SC-21, pp. 983-988, December 1986.
With the foregoing configuration, the conventional current driven D/A converter has noise occurring because of the charge injections caused by the unnecessarily large amplitude of the control voltage of the current switches of the current driven D/A converter, which becomes a factor of the performance degradation.
In addition, the large charge discharge current flows from the gate electrodes of the switching transistors into the ground or power supply terminal instantaneously when turning off the transistors. This causes noise in the ground voltage or in the power supply voltage, which offers a problem of the performance degradation of the D/A converter.
Furthermore, because of the variations in the threshold voltage Vth due to the substrate bias effect, the bias circuit of the conventional cascode connection current source must generate the bias voltage with leaving sufficient margin considering the fabrication variations in the current value and Vth. Thus, in the low voltage circuit or in the circuit with a small output voltage of the current source, a problem arises in that it is difficult to configure the bias circuit that meets the saturation conditions of the transistors.